Evaluation and Analysis of Heuristic Techniques for Vector Ordering of VLSI Test Sets

Vector ordering is an essential task in testing very large scale integration systems because it affects this process from two perspectives: 1) power consumption and 2) correlation among test data. The former feature is crucial and, if not properly controlled, may result in permanent failure of the device under test (DUT). The latter feature is also important because correlation is captured by coding schemes to efficiently compress test data and ease memory requirements of automatic test equipment (ATE) while reducing volume and lowering test application time. Vector ordering, however, is NP-complete. This paper presents an evaluation of different heuristic techniques for vector ordering using the 1985 and 1989 IEEE International Symposium on Circuits and Systems (ISCAS85 and ISCAS89, respectively) benchmark circuits in terms of run time and solution quality. For this application, it is shown that the best heuristic technique is not the one based on the famous Christofides or Lin-Kernighan criteria but on the multifragment technique. It has been shown that the selection of an appropriate heuristic can lead to an increase in the compression ratio of up to 178% and a reduction in the power consumption during test of up to 46%.