• DocumentCode
    1094126
  • Title

    Modeling Power Supply Noise in Delay Testing

  • Author

    Jing Wang ; Walker, D.M. ; Xiang Lu ; Majhi, A. ; Kruseman, B. ; Gronthoud, G. ; Villagra, L.E. ; van de Wiel, P.J.A. ; Eichenberger, S.

  • Author_Institution
    Texas A&M Univ., College Station
  • Volume
    24
  • Issue
    3
  • fYear
    2007
  • Firstpage
    226
  • Lastpage
    234
  • Abstract
    Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and
  • Keywords
    delays; electronic equipment testing; power electronics; power engineering computing; power supply quality; delay testing; excessive power supply noise; power network analysis; power noise analysis; power supply noise modeling; test compaction; CMOS technology; Circuit noise; Circuit testing; Compaction; Delay; Noise generators; Noise reduction; Power supplies; Semiconductor device noise; Voltage; compaction; delay test; filling; power supply noise model;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2007.76
  • Filename
    4288265
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1094126