Title :
Next-generation microvia and global wiring technologies for SOP
Author :
Sundaram, Venky ; Tummala, Rao R. ; Liu, Fuhan ; Kohl, Paul A. ; Li, Jun ; Bidstrup-Allen, Sue Ann ; Fukuoka, Yoshitaka
Author_Institution :
Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fDate :
5/1/2004 12:00:00 AM
Abstract :
As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-μm area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 μm diameter and lines and spaces of 25 μm. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for micro via wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 μm and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.
Keywords :
chemical mechanical polishing; dielectric thin films; electroless deposition; integrated circuit interconnections; integrated circuit packaging; printed circuits; chemical-mechanical polishing; conductor deposition; conductors; dielectric deposition; dielectric thin films; electroless copper plating; embedded passives; fine lines; global interconnect; global wiring technologies; microvia; printed wiring boards; system-in-a-package; system-on-a-package; ultralow-loss dielectrics; ultrathin-film dielectrics; Conducting materials; Conductors; Dielectric substrates; Dielectric thin films; High speed integrated circuits; Integrated circuit packaging; Space technology; Technological innovation; Throughput; Wiring; Conductors; PWB; SIP; SOP; embedded passives; fine lines; global interconnect; high speed; low-loss dielectrics; microvia; stacked vias; system-in-a-package; system-on-a-package; thin film;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2004.831890