DocumentCode :
1094428
Title :
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput
Author :
Ndai, Patrick ; Bhunia, Swarup ; Agarwal, Amit ; Roy, Kaushik
Author_Institution :
Purdue Univ, West Lafayette, IN
Volume :
57
Issue :
7
fYear :
2008
fDate :
7/1/2008 12:00:00 AM
Firstpage :
940
Lastpage :
951
Abstract :
Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units and allows more cycles for the slower units. We propose an associated priority scheduling strategy to schedule instructions in the functional units to maximize throughput. Simulation results on a set of benchmarks show that, by assigning a higher scheduling priority to faster units, we can achieve 18 percent improvement in performance on average with negligible design overhead.
Keywords :
instruction sets; microprocessor chips; processor scheduling; delay distribution; instruction scheduling; low-overhead design; operation frequency; priority scheduling; superscalar processors; within-die variation-aware scheduling; CMOS technology; Circuits; Degradation; Delay; Fluctuations; Frequency; Pipelines; Processor scheduling; Threshold voltage; Throughput; Scheduling; Superscalar Processors; Variable-cycle functional unit; process variation; speed binning.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2008.40
Filename :
4468699
Link To Document :
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