DocumentCode :
1094496
Title :
Optimization of breakdown voltage and on-resistance of VDMOS transistors
Author :
Darwish, Mohamed N. ; Board, Kenneth
Author_Institution :
University College of Swansea, Singleton Park, Swansea, U.K.
Volume :
31
Issue :
12
fYear :
1984
fDate :
12/1/1984 12:00:00 AM
Firstpage :
1769
Lastpage :
1773
Abstract :
The combined effect of the spacing between adjacent drain junctions, epilayer thickness, and resistivity in VDMOS transistors on both its breakdown voltage and 
product is investigated. It is shown that an increase in the breakdown voltage results as the junctions spacing is reduced. That gives a significant difference in the product when compared with results where this effect is ignored. A design optimization study is carried out to determine the parameters of a VDMOS transistor at 1000-V breakdown.
product is investigated. It is shown that an increase in the breakdown voltage results as the junctions spacing is reduced. That gives a significant difference in the product when compared with results where this effect is ignored. A design optimization study is carried out to determine the parameters of a VDMOS transistor at 1000-V breakdown.Keywords :
Conductivity; Design optimization; Doping profiles; Electric breakdown; Epitaxial layers; Helium; Immune system; Numerical simulation; P-n junctions; Poisson equations;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1984.21786
Filename :
1484071
Link To Document :
