DocumentCode
1094740
Title
Multiobjective placement of electronic components using evolutionary algorithms
Author
Deb, Kalyanmoy ; Jain, Prateek ; Gupta, Naveen Kumar ; Maji, Hemant Kumar
Author_Institution
Dept. of Mech. Eng., Indian Inst. of Technol. Kanpur, India
Volume
27
Issue
3
fYear
2004
Firstpage
480
Lastpage
492
Abstract
The optimal placement of electronic components on a printed circuit board is a well-studied optimization task. However, despite the involvement of multiple conflicting objectives, researchers have mainly used a single objective of minimizing the overall wire length or minimizing the overall heat generation or minimizing the overall time delay in its functioning. In this paper, the problem is treated as a two-objective optimization problem of minimizing the overall wire length and minimizing the failure-rate of the board arising due to uneven local heat accumulation. The proposed strategy uses a novel representation procedure and a multiobjective evolutionary algorithm capable of finding multiple Pareto-optimal solutions simultaneously. Moreover, the flexibility and efficacy of the proposed strategy have been demonstrated by simultaneously optimizing the placement of components and the layout of the board. The convergence and the extent of spread obtained in the solutions reliably by repetitive applications of the proposed procedure should encourage further application of the approach to more complex placement design problems.
Keywords
Pareto distribution; VLSI; circuit optimisation; printed circuit layout; complex placement design problems; electronic components; evolutionary algorithms; failure-rate minimization; heat accumulation; heat generation minimization; multiobjective evolutionary algorithm; multiobjective placement; multiple Pareto-optimal solutions; multiple conflicting objectives; optimal placement; optimization task; printed circuit board; representation procedure; time delay minimization; two-objective optimization problem; very large scale integration placement; wire length minimization; Delay effects; Electronic components; Evolutionary computation; Genetic algorithms; Helium; Integrated circuit interconnections; Minimization; Printed circuits; Very large scale integration; Wire; Evolutionary algorithms; Pareto-optimal solutions; VLSI; heat generation; multiobjective optimization; placement; very large scale integration; wire-length;
fLanguage
English
Journal_Title
Components and Packaging Technologies, IEEE Transactions on
Publisher
ieee
ISSN
1521-3331
Type
jour
DOI
10.1109/TCAPT.2004.831775
Filename
1331543
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