Title :
The Design And Implementation of the MC68851 Paged Memory Management Unit
Author :
Cohen, Brad ; McGarity, Ralph
Author_Institution :
Motorola Microprocessor Products Division
fDate :
4/1/1986 12:00:00 AM
Abstract :
Pipelining, microsequencer start-up in parallel with bus arbitration, and a fully associative translation cache enhanced the performance of this 32-bit memory management device.
Keywords :
Control systems; Coprocessors; Environmental management; Memory management; Microprocessors; Operating systems; Pipeline processing; Signal processing;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.1986.304739
