A modular T-mode design approach for analog neural network hardware implementations

Author

Linares-Barranco, Bernabé ; Sánchez-Sinencio, Edgar ; Rodríguez-Vázquez, Angel ; Huertas, José L.

Author_Institution

Centro Nacional de Microelectronica, Sevilla, Spain

Volume

27

Issue

5

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

701

Lastpage

713

Abstract

A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART 1 network, or a constrained optimization network. Experimentally measured results from CMOS 2-μm double-metal, double-polysilicon prototypes (MOSIS) are presented

Keywords

CMOS integrated circuits; content-addressable storage; neural nets; 2 micron; ART 1 network; CMOS; Hopfield network; MOSIS; analog neural network; bidirectional associative memory network; constrained optimization network; double-metal; double-polysilicon; hardware implementations; interconnection strategy; modular T-mode design approach; transconductance-mode; winner-take-all network; Associative memory; Constraint optimization; Hopfield neural networks; Integrated circuit interconnections; Magnesium compounds; Neural network hardware; Neural networks; Prototypes; Real time systems; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.133157

Filename

133157