Serendipitous SEU hardening of resistive load SRAMs

Author

Koga, R. ; Kirshman, J.F. ; Pinkerton, S.D. ; Hansel, S.J. ; Crawford, K.B. ; Crain, W.R.

Author_Institution

Aerosp. Corp., Los Angeles, CA, USA

Volume

43

Issue

3

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

931

Lastpage

935

Abstract

High and low resistive load versions of Micron Technology´s MT5C1008C (128K×8) and MT5C2561C (256K×1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors was observed for the low resistive load SRAMs, which also exhibited a “1”→“0” to “0”→“1” bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations

Keywords

CMOS memory circuits; SRAM chips; integrated circuit testing; ion beam effects; radiation hardening (electronics); 1024 kbit; 256 kbit; CMOS cells; MT5C1008C; MT5C2561C; Micron Technology; SEU cross-section temperature dependence; SEU susceptibility; SRAM testing; error bit polarity effect; multiple-bit errors; resistive load SRAMs; serendipitous SEU hardening; upset mechanisms; Aerospace testing; CMOS memory circuits; CMOS technology; Computer errors; Computer simulation; MOSFETs; Random access memory; SRAM chips; Single event upset; Variable structure systems;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.510736

Filename

510736