Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance

A CMOS off-chip signal driver that achieves a 2.5-3 times smaller di/dt noise than the conventional design while not incurring the penalty of signal delay is described. It minimizes L di/dt effects by reducing the output signal swing by about a factor of 2 and by providing a controlled ramp rate for the output current. The circuit has a nearly constant output resistance for source termination of transmission lines, and includes a receiver designed for the smaller signal swing. Simulations show a driver-receiver delay of 3 ns for a 7.5-cm line on a multichip package with a peak di/dt of only 12 mA/ns. Driver-receiver delay and noise measurements are also presented