Title :
Design and optimization of buffer chains and logic circuits in a BiCMOS environment
Author :
Elrabaa, Muhammad S. ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
5/1/1992 12:00:00 AM
Abstract :
The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied
Keywords :
BIMOS integrated circuits; buffer circuits; integrated logic circuits; logic design; logic gates; many-valued logics; BiCMOS environment; CML; buffer chains; circuit design; complex logic gates; current mode logic; delay expressions; design guidelines; multi level logic circuits; multistage mixed CMOS/BiCMOS buffers; optimization; speedup contours; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Delay; Design methodology; Design optimization; Logic circuits; Logic design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
