A monolithic multigigabit/second DCFL GaAs decision circuit

A GaAs integrated circuit has been designed and fabricated to regenerate digital data at gigabit per second rates. The circuit architecture is direct-coupled FET logic (DCFL), and the fabrication is by self-aligned etched gate on CVD epitaxial material. The circuit includes a moderate-gain input amplifier with threshold adjustment, a clocked D flip-flop for data sampling and storage, and an output buffer for driving low impedance transmission lines. Dynamic performance measurements include correct regeneration of pseudorandom data at 2.0 Gbit/s, the maximum allowed by available instrumentation, and 1010... data at 2.4 Gbit/s. Rise/fall times below 150 ps into 50 Ω were observed. A minimum gate delay of 17.8 ps and a maximum toggle frequency of 3.8 GHz were measured with associated ring oscillator and binary frequency divider circuits, respectively.