Title :
Planar fully ion implanted InP power junction FET´s
Author :
Boos, J.B. ; Binari, S.C. ; Kelner, G. ; Thompson, P.E. ; Weng, T.H. ; Papanicolaou, N.A. ; Henry, R.L.
Author_Institution :
Naval Research Laboratory, Washington, DC
fDate :
7/1/1984 12:00:00 AM
Abstract :
This letter reports on the fabrication and performance of planar all ion-implanted 1.0-µm gate length InP power junction field effect transistors (JFET´s). The devices were fabricated utilizing n+ implantation, a AuZn/TiW/Au gate metallization, and an n+ drain ledge. At 4.5 GHz, the 300-µm gate width JFET´s exhibited maximum insertion gains of up to 13 dB and scaled output powers as high as 1 W/mm with 3-dB gain.
Keywords :
Alloying; FETs; Fabrication; Gallium arsenide; Gold; Indium phosphide; MISFETs; Metallization; Millimeter wave technology; Power generation;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1984.25915