Title :
Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor
Author :
Aguirre, M.A. ; Tombs, J.N. ; Muoz, Fernando ; Baena, V. ; Guzman, H. ; Napoles, J. ; Torralba, A. ; Fernandez-Leon, A. ; Tortosa-Lopez, F. ; Merodio, D.
Author_Institution :
Univ. de Sevilla, Sevilla
Abstract :
VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.
Keywords :
VLSI; aerospace components; circuit simulation; flip-flops; FT-UNSHADES; SEU emulator; VLSI circuits; flip-flops; multi-bit flips; selective protection analysis; Circuit faults; Circuit testing; Costs; Hardware; Production; Protection; Protocols; Redundancy; Silicon; Very large scale integration; ASIC; FPGA reconfiguration; FPGA-based emulation; Fault injection; multi-bit upset; single event upset (SEU);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2007.895550