DocumentCode
1098341
Title
Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations
Author
Giot, Damien ; Roche, Philippe ; Gasiot, Gilles ; Harboe-Sorensen, Reno
Author_Institution
Central CAD & Design Solutions Group, Crolles
Volume
54
Issue
4
fYear
2007
Firstpage
904
Lastpage
911
Abstract
SEU and MBU cross-sections are measured with heavy ions for commercial 90 nm single port and dual port SRAMs. SEU and MBU rates are discussed as a function of the LET and beam tilt. A new sensitive area devoted to MBU is computed with full 3D TCAD simulations on single and adjacent memory cells.
Keywords
CMOS memory circuits; SRAM chips; ion beam effects; technology CAD (electronics); 3D TCAD simulations; dual port SRAM; heavy ions testing; memory cells; multiple-bit upset analysis; single event upset; single port SRAM; size 90 nm; Analytical models; Circuit simulation; Circuit testing; Computational modeling; Design automation; MOSFETs; Neutrons; Semiconductor device measurement; Single event upset; Space technology; Charge sharing; MOS transistor; critical charge; heavy ions; multiple-bit upset; sensitive area; silicon; single-event upset;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2007.902360
Filename
4291734
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