Title :
1.0-µm n-well CMOS/bipolar technology
Author :
Momose, Hiroshi ; Shibata, Hideki ; Saitoh, Shinji ; Miyamoto, Jun´ichi ; Kanzaki, Kohichi ; Kohyama, Susumu
Author_Institution :
Toshiba Corporation, Kawasaki, Japan
fDate :
2/1/1985 12:00:00 AM
Abstract :
High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n+-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n+-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.
Keywords :
Bipolar transistors; CMOS process; CMOS technology; Circuits; Degradation; Fabrication; Hot carriers; MOS devices; Ring oscillators; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.21932