DocumentCode
1098729
Title
An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI
Author
Okada, Yutaka ; Kaneko, Kenji ; Kudo, Satoshi ; Yamazaki, Kouichi ; Okabe, Takahiro
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
32
Issue
2
fYear
1985
fDate
2/1/1985 12:00:00 AM
Firstpage
232
Lastpage
236
Abstract
A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I2L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (
m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n+buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.
m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n+buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.Keywords
Analog circuits; Analog-digital conversion; Bipolar transistors; CMOS process; CMOS technology; Epitaxial layers; MOS devices; MOSFETs; Substrates; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1985.21934
Filename
1484681
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