Two-dimensional analysis of writing mechanisms for a taper isolated RAM cell

Writing mechanisms for a taper isolated RAM cell are quantitatively analyzed and a design guide is described. A two-dimensional numerical analysis shows that two different writing mechanisms exist, depending on the device structure at the channel edges. One is a parasitic p-channel MOSFET action in the LOCOS taper region. The other is a vertical p-n-p bipolar-transistor action. In the cell using the parasitic MOSFET action, the inhibit "0" writing characteristic is poor, because the substrate potential for the parasitic p-MOSFET is not controllable. Selective "1" writing is realized only for a short-channel cell, by modulating the potential under the p-layer with a source (word line) potential. A complete memory cell operation can be achieved using accurate device design and trench isolation.