Title :
Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors
Author :
Valderas, Mario García ; Peronnard, Paul ; Ongil, Celia López ; Ecoffet, Robert ; Bezerra, Francoise ; Velazco, Raoul
Author_Institution :
Univ. Carlos III de Madrid, Madrid
Abstract :
This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The code emulated upset (CEU) approach allows fault injection in processor memories (caches and register files), while the FPGA autonomous emulation approach allows fault injection in processor flip-flops. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.
Keywords :
error analysis; fault simulation; field programmable gate arrays; FPGA autonomous emulation approach; SEU; code emulated upset; digital processors; error rate prediction; fault injection sessions; Circuit faults; Emulation; Error analysis; Field programmable gate arrays; Flip-flops; Particle measurements; Registers; Single event transient; Single event upset; System testing; FPGA emulation; Fault injection; SEU; fault tolerance;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2007.893871
