Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors

This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The code emulated upset (CEU) approach allows fault injection in processor memories (caches and register files), while the FPGA autonomous emulation approach allows fault injection in processor flip-flops. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.