Suppression of the boron penetration induced Si/SiO/sub 2/ interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Author

Wu, Shye Lin ; Lee, Chung Len ; Lei, Tan Fu ; Chen, J.F. ; Chen, L.J.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

15

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

160

Lastpage

162

Abstract

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO/sub 2/ interface. An atomically flat Si/SiO/sub 2/ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p/sup +/ poly-Si gate MOS devices even with the annealing temperature as high as 1000/spl deg/C.<>

Keywords

amorphous semiconductors; annealing; boron; elemental semiconductors; insulated gate field effect transistors; ion implantation; semiconductor thin films; semiconductor-insulator boundaries; silicon; 1000 C; B penetration suppression; Si; Si substrate; Si-SiO/sub 2/; Si/SiO/sub 2/ interface degradation; annealing temperature; atomically flat Si/SiO/sub 2/ interface; p/sup +/ poly-Si gate MOS devices; pMOSFET; stacked amorphous Si film gate; stacked gate structure; thin gate oxide; threshold voltage shift; Annealing; Boron; Capacitors; Degradation; MOSFET circuits; Semiconductor films; Substrates; Synthetic aperture sonar; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.291600

Filename

291600