An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain

The computational complexity of the MPEG-2 to H.264/AVC transcoder, in particular the encoder, is technically challenging, but it can be reduced by reusing the information accessible in the decoding process. A low-latency mode decision algorithm performed in transform domain within the MPEG-2 decoder is proposed. The encoder stage contains two mutually exclusive intra prediction algorithms of block sizes 4x4 and 16x16 sharing the hardware logic. The shared intra prediction unit is supported by an on-chip memory organization. The proposed architecture is implemented on FPGA development board. Its implementation supports high throughputs that correspond to a real-time processing of a variety of video resolutions including QFHD 2160p at 30 fps. Furthermore, the minimal required frequency for CIF, SD and HD1080p resolutions are significantly reduced compared to the state of the art¹.