Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance

Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance under a voltage ramp is analyzed. It is found that even when the external voltage is ramping up, α1+ α2> 1, and both bipolar transistors are biased in the forward-active region, the circuit can still dynamically recover internally due to the inherently nonlinear character of the voltage-dependent substrate-well junction capacitance. Numerical results for the cases of linearly graded and step junctions are presented and some optimal conditions for preventing transient latchup are briefly discussed.