High-Voltage CMOS ESD and the Safe Operating Area

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V _t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I _t2. For the first time, the evolution of V _t1 as a function of the number of TLP pulses and their magnitude is shown. Furthermore, some high-voltage clamps that are robust on their own are shown to walk-in in certain circuit environments that present high capacitance. The physical mechanism for this leakage enhancement and trigger-voltage walk-in has been established through failure analysis to be consistent with melt filament growth perhaps aided by metal migration. A simple phenomenological model is proposed to explain this behavior. Finally, the ability to avoid such V _t1 collapse in SCRLDMOS through simple layout changes is shown.