Title :
A single chip speech synthesizer using a switched-capacitor multiplier
Author :
Gregorian, Roubik ; Amir, Gideon
Author_Institution :
American Microsystems, Inc., Santa Clara, CA
fDate :
2/1/1983 12:00:00 AM
Abstract :
A single chip speech synthesizer was designed using a switched-capacitor multiplier to implement the LPC algorithm. The chip contains the LPC-10 filter, 20 kbit ROM, all control logic, a three-pole switched-capacitor low-pass filter, and an audio amplifier capable of driving a speaker directly. The chip was fabricated in 5 μm CMOS technology and is 218 mils on the side.
Keywords :
Bit rate; CMOS technology; Linear predictive coding; Low pass filters; Read only memory; Resonator filters; Silicon; Speech analysis; Speech synthesis; Synthesizers;
Journal_Title :
Acoustics, Speech and Signal Processing, IEEE Transactions on
DOI :
10.1109/TASSP.1983.1164008
