DocumentCode :
1100061
Title :
Power comparison between high-speed electrical and optical interconnects for interchip communication
Author :
Cho, Hoyeol ; Kapur, Pawan ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Volume :
22
Issue :
9
fYear :
2004
Firstpage :
2021
Lastpage :
2033
Abstract :
An I/O bandwidth commensurate with a dramatically increasing on-chip computational capability is highly desirable. Achieving this goal using board-level copper interconnects in the future will become increasingly challenging owing to severe increase in high-frequency, skin-effect and dielectric loss, noise due to crosstalk, impedance mismatch, and package reflections. The solutions designed to overcome these deleterious effects require complex signal processing at the interconnect endpoints, which results in a larger power and area requirement. Optical interconnects offer a powerful alternative, potentially at a lower power. Prior work in comparing the two technologies has entailed overly simplified assumptions pertaining to either the optical or the electrical system. In this paper, we draw a more realistic power comparison with respect to the relevant parameters such as bandwidth, interconnect length and bit error rate (BER) by capturing the essential complexity in both types of interconnect systems. At the same time, we preserve the simplicity by using mostly analytical models, verified by SPICE simulations where possible. We also identify critical device and system parameters, which have a large effect on power dissipation in each type of interconnect, while quantifying the severity of their impact. For optical interconnect, these parameters are detector and modulator capacitance, responsivity, coupling efficiency and modulator type; whereas, in the case of electrical system, the critical parameters include receiver sensitivity/offset and impedance mismatch. Toward this end, we first present an optimization scheme to minimize optical interconnect power and quantify its performance as a function of future technology nodes. Next, on the electrical interconnect side, we examine the power dissipation of a state-of-the-art electrical interconnect, which uses simultaneous bidirectional signaling with transmitter equalization and on-chip noise cancellation. Finally, we draw extensive comparisons between optical and electrical interconnects. As an example, for bandwidth of 6 Gb/s at 100 nm technology node, lengths greater than the critical length of about 43 cm yields lower power in optical interconnects. This length becomes lower (making optics more favo- rable) with higher data rates and lower bit error rate requirement.
Keywords :
dielectric losses; digital integrated circuits; error statistics; high-speed optical techniques; integrated circuit modelling; optical fibre communication; optical interconnections; optical transmitters; optimisation; skin effect; SPICE simulations; bidirectional signaling; bit error rate; coupling efficiency; detector capacitance; dielectric attenuation; electrical interconnects; high-speed interconnects; impedance mismatch; interchip communication; interconnect systems; modulator capacitance; noise modeling; on-chip noise cancellation; optical interconnects; optimization; power comparison; power dissipation; power modeling; receiver sensitivity/offset; skin effect attenuation; transimpedance amplifier; transmitter equalization; Bandwidth; Bit error rate; Dielectric losses; Optical interconnections; Optical noise; Optical receivers; Optical sensors; Optical signal processing; Optical transmitters; Power system interconnection; Dielectric and skin effect attenuation; electrical interconnect; equalization; interchip communication; modulator; noise modeling; optical interconnect; power comparison; power modeling; simultaneous bidirectional signaling; transimpedance amplifier;
fLanguage :
English
Journal_Title :
Lightwave Technology, Journal of
Publisher :
ieee
ISSN :
0733-8724
Type :
jour
DOI :
10.1109/JLT.2004.833531
Filename :
1333103
Link To Document :
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