Title :
A 300 nW, 15 ppm/
C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
Author :
Ueno, Ken ; Hirose, Tetsuya ; Asai, Tetsuya ; Amemiya, Yoshihito
Author_Institution :
Dept. of Electr. Eng., Hokkaido Univ., Sapporo
fDate :
7/1/2009 12:00:00 AM
Abstract :
A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
Keywords :
CMOS integrated circuits; MOSFET; large scale integration; MOSFET circuits; low-power CMOS voltage reference; power 0.3 muW; power supply rejection ratio; power-aware LSI; size 0.35 mum; temperature -20 degC to 80 degC; voltage 1.4 V to 3 V; voltage 745 mV; CMOS process; CMOS technology; MOSFET circuits; Power dissipation; Power supplies; Resistors; Standards development; Temperature distribution; Temperature sensors; Threshold voltage; CMOS; die-to-die variation; power-aware LSIs; process variation; subthreshold; ultra-low power; voltage reference; weak inversion;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2021922