DocumentCode
1100238
Title
Low-Power 32-bit Dual-MAC 120 
W/MHz 1.0 V icyflex1 DSP/MCU Core
Author
Arm, Claude ; Gyger, Stève ; Masgonty, Jean-Marc ; Morgan, Marc ; Nagel, Jean-Luc ; Piguet, Christian ; Rampogna, Flavio ; Volet, Patrick
Author_Institution
CSEM, Neuchatel
Volume
44
Issue
7
fYear
2009
fDate
7/1/2009 12:00:00 AM
Firstpage
2055
Lastpage
2064
Abstract
A low-power programmable processor named icyflex1 was designed combining features of a digital signal processor (DSP) and a micro-controller unit (MCU). Implemented as a synthesizable VHDL software intellectual property core, the processor implements a broad range of power saving features including its customizable architecture and reconfigurable instruction set. Its performance is compared with other processors from the market and values are given for its integration in a 180 nm technology. The processor targets applications with tight power consumption constraints and correspondingly significant processing performance.
Keywords
digital signal processing chips; hardware description languages; integrated circuit design; low-power electronics; microcontrollers; DSP-MCU core; digital signal processor; icyflex1 design; low-power dual-MAC operation; low-power programmable processor; micro-controller unit; reconfigurable instruction set; size 180 nm; synthesizable VHDL software; voltage 1 V; Algorithm design and analysis; Clocks; Computer architecture; Data processing; Digital signal processing; Digital signal processors; Energy consumption; Pipeline processing; Reduced instruction set computing; Signal processing algorithms; Customizable; RISC; digital signal processor (DSP); icyflex; microcontroller; processor architecture; run-time reconfigurable; ultra low power;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2021924
Filename
5109790
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