A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Tomlinson-Harashima (TH) precoding is a transmitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an infinite impulse response (IIR) filter with modulo (MOD)-based amplitude limitation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept simple. To increase the data rate, we propose the application of pipelining and half-rate operation to the ISI subtraction in the equalizer´s feedback path. A TH equalizer with 8 taps, 6 bit resolution, and 2-PAM/4-PAM support has been implemented in 22-nm silicon-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction techniques allow us to equalize 34-cm-long PCB traces having 12-dB loss with 7 × ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured efficiency of the 145 μm× 115 μm transmitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 μW/Gbaud per 1% increase of the equalization tap weights.