Design consideration and performance of a new MOS imaging device

The design considerations and performance of a new MOS imaging device with novel random noise suppression (RANS) circuits are described. This device consists of 492 × 388 photodiodes, a vertical shift register, and a horizontal BCD register integrated in p-wells. The RANS circuits accelerate the charge-transfer speed from vertical signal lines to a horizontal BCD register with 98-percent efficiency. They also decrease the effective signal line capacitance, so noise due to the transfer MOS switches is suppressed to obtain a high signal-to-noise ratio of 46 dB at a standard scene illumination of 180 lx (F1.4) with no image lag and blooming. Sweep out operation for the smear charge accumulated in the vertical signal lines realizes a sufficient signal-to-smear ratio of 69 dB at 1/10 vertical scene illumination.