• DocumentCode
    1101059
  • Title

    Computer-Aided Test Generation for Four-Phase MOS LSI Circuits

  • Author

    Yen, Yao Tung

  • Author_Institution
    IEEE
  • Issue
    10
  • fYear
    1969
  • Firstpage
    890
  • Lastpage
    894
  • Abstract
    In this paper a practical approach to generate fault detection tests for four-phase MOS LSI circuits is discussed. Emphasis is given to a computer aid on the generation of both primary output and primary input test sequences. A technique to preset the circuit to predictable logic levels is presented.
  • Keywords
    Computer aid, four-phase, LSI, MOS, test generation.; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Computer simulation; Large scale integration; Logic arrays; Logic circuits; Logic gates; Computer aid, four-phase, LSI, MOS, test generation.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1969.222543
  • Filename
    1671136
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1101059