Abstract :
In this paper a practical approach to generate fault detection tests for four-phase MOS LSI circuits is discussed. Emphasis is given to a computer aid on the generation of both primary output and primary input test sequences. A technique to preset the circuit to predictable logic levels is presented.
Keywords :
Computer aid, four-phase, LSI, MOS, test generation.; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Computer simulation; Large scale integration; Logic arrays; Logic circuits; Logic gates; Computer aid, four-phase, LSI, MOS, test generation.;
