DocumentCode :
1101166
Title :
Logical Design Using Shift Registers
Author :
Davis, W. Alan
Issue :
10
fYear :
1969
Firstpage :
958
Lastpage :
960
Abstract :
This correspondence presents a logical design procedure for feedback shift registers, which permits the gating of a common clock signal.
Keywords :
Logical design, sequential machine, shift register, state assignment.; Circuits; Clocks; Delay; Feedback; Hardware; Packaging; Process design; Shift registers; Signal design; Synchronization; Logical design, sequential machine, shift register, state assignment.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1969.222554
Filename :
1671147
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1101166
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