A 1.3-ns 32-word×32-bit three-port BiCMOS register file

Author

Chao, Chin-Chieh ; Wooley, Bruce A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

31

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

758

Lastpage

766

Abstract

This paper describes a CMOS multiport static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word×32 bit three-port register file has been designed and implemented using this cell. The register file was fabricated in a 0.6-μm BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20°C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz

Keywords

BiCMOS memory circuits; multiport networks; 0.6 micron; 1.3 ns; 100 MHz; 20 C; 3.3 V; 32 bit; 650 mW; CMOS multiport static memory cell; ECL-compatible I/O circuits; current-switching bipolar peripheral circuits; memory array; minimum write enable pulse width; pin-to-pin access time; three-port BiCMOS register file; BiCMOS integrated circuits; CMOS memory circuits; CMOS technology; Power dissipation; Power supplies; Pulsed power supplies; Registers; Space vector pulse width modulation; Time measurement; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.511018

Filename

511018