Multi-input strobed analogue comparator

The architecture presented combines a cross-coupled `winner takes all´ circuit with a multi-input digital latch. Only one of the digital outputs is a logic `one´, corresponding to the largest analogue input. A five-input prototype was built using a 2 μm CMOS process. The 300×280 μm² circuit dissipates 1 mW from a single 5 V supply at a maximum clock frequency of 10 MHz