Title :
Gallium arsenide pseudo-dynamic latched logic
Author :
López, J.F. ; Eshraghian, K. ; Sarmiento, R. ; Núñez, A.
Author_Institution :
Centre for Appl. Microelectron., Las Palmas de Gran Canaria Univ., Spain
fDate :
7/18/1996 12:00:00 AM
Abstract :
A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems
Keywords :
III-V semiconductors; field effect logic circuits; gallium arsenide; integrated circuit design; integrated circuit noise; logic gates; pipeline processing; GaAs; PDLL; charge degradation; compact pipeline systems; complex gate design; logic families; power dissipation; pseudo-dynamic latched logic; self-latched; storage nodes;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960926
