DocumentCode
1101831
Title
Gallium arsenide pseudo-dynamic latched logic
Author
López, J.F. ; Eshraghian, K. ; Sarmiento, R. ; Núñez, A.
Author_Institution
Centre for Appl. Microelectron., Las Palmas de Gran Canaria Univ., Spain
Volume
32
Issue
15
fYear
1996
fDate
7/18/1996 12:00:00 AM
Firstpage
1353
Lastpage
1354
Abstract
A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems
Keywords
III-V semiconductors; field effect logic circuits; gallium arsenide; integrated circuit design; integrated circuit noise; logic gates; pipeline processing; GaAs; PDLL; charge degradation; compact pipeline systems; complex gate design; logic families; power dissipation; pseudo-dynamic latched logic; self-latched; storage nodes;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960926
Filename
511112
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