Title :
A charge recycle refresh for Gb-scale DRAM´s in file applications
Author :
Kawahara, Takayuki ; Kawajiri, Yoshiki ; Horiguchi, Masashi ; Akiba, Takesada ; Kitsukawa, Goro ; Kure, Tokuo ; Aoki, Masakazu
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
6/1/1994 12:00:00 AM
Abstract :
A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells
Keywords :
DRAM chips; VLSI; electric charge; file servers; 0.25 μm technology; 0.25 mum; 64 kb test chip; Gb-scale DRAM´s; amplification; charge recycle refresh; data-line current dissipation; file applications; half amplification; low-power DRAM data-retention; memory arrays; multi-array activation; peak current; power supply line; voltage bounce; Circuits; Helium; Leakage current; Personal digital assistants; Power dissipation; Power supplies; Random access memory; Recycling; Testing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
