Title :
Impact of clock slope on true single phase clocked (TSPC) CMOS circuits
Author :
Larsson, Patrik ; Svensson, Christer
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Inst. of Technol., Sweden
fDate :
6/1/1994 12:00:00 AM
Abstract :
Clocked digital circuits are sensitive to changes of the input signals close to the clock transitions. Non ideal properties of the clock transition, such as slope, make timing requirements more complicated. Here we present methods, quantitative limits and clock buffer requirements by studying clock slope impact on TSPC circuits. The investigation is based on SPICE simulations of edge-triggered D flip-flops and latches, implemented in the TSPC technique. The simulation results were also verified by measurements on 2-μm CMOS prescalers
Keywords :
CMOS integrated circuits; SPICE; circuit analysis computing; clocks; flip-flops; integrated logic circuits; synchronisation; 2 micron; CMOS circuits; CMOS prescalers; SPICE simulations; TSPC technique; clock buffer requirements; clock slope; clocked digital circuits; edge-triggered D flip-flops; latches; true single phase clocked circuits; Circuit simulation; Clocks; Digital circuits; Flip-flops; Latches; MOS devices; MOSFETs; SPICE; Signal generators; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
