Title :
CMOS four-quadrant multiplier using bias feedback techniques
Author :
Liu, Shen-Iuan ; Hwang, Yuh-Shyan
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan
fDate :
6/1/1994 12:00:00 AM
Abstract :
A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of ±5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over ±1 V. The results will be useful in analog signal processing applications
Keywords :
CMOS integrated circuits; analogue processing circuits; linear integrated circuits; multiplying circuits; CMOS four-quadrant multiplier; analog signal processing; bias feedback techniques; linear range; linearity error; Circuit analysis; Degradation; Dynamic range; Feedback circuits; Frequency; Linearity; MOSFETs; Power supplies; Signal processing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
