• DocumentCode
    1102299
  • Title

    A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

  • Author

    Wordeman, Matthew R. ; Schweighart, April M. ; Dennard, Robert H. ; Sai-Halasz, George ; Molzen, Walter W.

  • Author_Institution
    IBM Thomas J. Watson Research Center, Yorktown Heights, NY
  • Volume
    32
  • Issue
    11
  • fYear
    1985
  • fDate
    11/1/1985 12:00:00 AM
  • Firstpage
    2214
  • Lastpage
    2223
  • Abstract
    Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET´s, including a study of nonscaling effects and their impact on the device and circuit design.
  • Keywords
    Circuit synthesis; Delay; Fabrication; Integrated circuit technology; Integrated circuit yield; Lithography; MOS devices; MOSFET circuits; Power dissipation; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1985.22260
  • Filename
    1485006