Title :
On the parasitic capacitances of multilevel parallel metallization lines
Author :
Taylor, Clayborne D. ; Elkhouri, George N. ; Wade, Thomas E.
Author_Institution :
Mississippi State University, Starkville, MS
fDate :
11/1/1985 12:00:00 AM
Abstract :
A versatile and powerful finite-difference solution technique is developed for determining the capacitances between arrays of closely spaced parallel conductors. Results are presented for configurations typical of multilevel VLSI structures.
Keywords :
Conductors; Delay; Finite difference methods; Finite element methods; Laplace equations; Metallization; Parasitic capacitance; Sparse matrices; Switching circuits; Very large scale integration;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.22287
