DocumentCode :
1102785
Title :
Designs of low stress I/O pin attach structures
Author :
Shih, D.-Y. ; Palmateer, P. ; Fu, Y. ; Kim, J. ; Kapur, S. ; Arnold, A. ; Brofman, P. ; Ghosal, B. ; Waldman, D. ; Hayunga, P. ; Pasco, R. ; Cvikevich, S. ; Corso, J. ; Advocate, G.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
15
Issue :
3
fYear :
1992
fDate :
6/1/1992 12:00:00 AM
Firstpage :
369
Lastpage :
377
Abstract :
Three low-stress pin attachment structures were developed for the glass ceramic-copper multilayer ceramic (MLC) packaging technology used in IBM ES 9000 processors. The structures include the multilayer thin-film I/O pads, taper-headed pin and low-stress solder as the joining alloy. All of them were shown to reduce the pin-joint stress significantly and, consequently, are more compatible with the glass-ceramic module. The authors summarize both experimental and finite-element analysis studies to optimize the stress of the pin-attach system such that the pins can be joined to the glass-ceramic MLC with good reliability. The design goal was to have a pin-joint structure in which the ceramic and the pin-joint will survive a pin-pull test up to 10 lbs with a repairable pin-shank failure mode. The combined stresses generated from the braze, pin loading, and I/O pad should not exceed the fracture strength of the ceramic substrate. Finite-element modeling identified high-stress regions and possible failure modes of each pin joint design. The three approaches taken to reduce the stress of the pin-joint are described
Keywords :
design engineering; finite element analysis; packaging; I/O pad; I/O pin attach structures; IBM ES 9000 processors; braze; combined stresses; experimental studies; failure modes; finite-element analysis studies; glass-ceramic MLC; glass-ceramic module; high-stress regions; joining alloy; low-stress pin attachment structures; low-stress solder; metal ceramic bonding; multilayer ceramic; multilayer thin-film I/O pads; packaging technology; pin joint design; pin loading; pin-grid arrays; pin-joint stress; pin-pull test; repairable pin-shank failure mode; taper-headed pin; thermal conduction module; Ceramics; Finite element methods; Glass; Nonhomogeneous media; Packaging; Pins; Stress; Substrates; Testing; Transistors;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/33.148505
Filename :
148505
Link To Document :
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