DocumentCode :
1102855
Title :
Methods Used in an Automatic Logic Design Generator (ALERT)
Author :
Friedman, Theodore D. ; Yang, Sih-chin
Author_Institution :
IEEE
Issue :
7
fYear :
1969
fDate :
7/1/1969 12:00:00 AM
Firstpage :
593
Lastpage :
614
Abstract :
The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits.
Keywords :
Architecture, automatic logic generation, compiler of computers, design automation, high-level computer description, Iverson notation, structural implementation of algorithms.; Automatic control; Automatic logic units; Circuits; Computer architecture; Design automation; Documentation; Equations; High level languages; Logic design; Manufacturing automation; Architecture, automatic logic generation, compiler of computers, design automation, high-level computer description, Iverson notation, structural implementation of algorithms.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1969.222727
Filename :
1671320
Link To Document :
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