Performance analysis of multilevel bus networks for hierarchical multiprocessors

A multiple bus system provides more bandwidth and a high degree of fault tolerance than a single bus system. But such a system becomes very expensive for a large number of processors and memory modules, due to the requirement of too many connections (switches). Lang (1983) proposed a different bus-based system, known as the partial multiple bus system, which requires a lower number of connections than a multiple bus system, but with a slight degradation in system performance. This paper presents a new type of bus-based system, called the multilevel bus system. Such a bus architecture can be used to design hierarchical multiprocessors. This bus-based system requires significantly less connections than multiple and partial multiple bus systems. This system is very cost-effective, as compared to multiple and partial multiple bus systems, when there exists some locality in the computations. Analytical and simulation models have been developed to determine the performance of both synchronous and asynchronous multilevel bus systems. The results obtained from the analysis show that a multilevel bus system performs fairly close to other bus-based systems for the hierarchical reference (HR) model. In the HR model, a processor accesses its nearest memory modules more frequently than other memory modules