Title :
Ultra-low power subthreshold current-mode logic utilising PMOS load device
Author :
Tajalli, A. ; Vittoz, E. ; Leblebici, Y. ; Brauer, E.J.
Author_Institution :
Swiss Fed. Inst. of Technol., Lausanne
Abstract :
A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18 mum CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1 nA, achieving sufficiently high gain ( > 3) over a wide frequency range.
Keywords :
CMOS logic circuits; MOS logic circuits; current-mode logic; logic design; low-power electronics; CMOS technology; MOS current-mode logic circuits; PMOS; size 0.18 mum; ultra-low bias currents;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20071208
