A semi-static complementary gain cell technology for sub-1 V supply DRAM´s

A new semi-static complementary gain cell for future low power DRAM´s has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 μm² cell size is achieved by using a 0.25 μm design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography