• DocumentCode
    1103355
  • Title

    The ILLIAC IV Processing Element

  • Author

    Davis, Robert L.

  • Author_Institution
    IEEE
  • Issue
    9
  • fYear
    1969
  • Firstpage
    800
  • Lastpage
    816
  • Abstract
    This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE´s, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc.
  • Keywords
    Computer arithmetic, ILLIAC IV, medium-scale integration, parallel processing.; Broadcasting; Clocks; Computer aided instruction; Decoding; Digital arithmetic; Logic; Parallel processing; Process design; Registers; Routing; Computer arithmetic, ILLIAC IV, medium-scale integration, parallel processing.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1969.222777
  • Filename
    1671370
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1103355