DocumentCode :
1103464
Title :
Process and device optimization of an analog complementary bipolar IC technology with 5.5-GHz fT pnp transistors
Author :
Yamaguchi, Tadanori ; Archer, Timothy M. ; Johnston, Roger E. ; Lee, June S.
Author_Institution :
Microelectron., Tektronix Inc., Beaverton, OR, USA
Volume :
41
Issue :
6
fYear :
1994
fDate :
6/1/1994 12:00:00 AM
Firstpage :
1019
Lastpage :
1026
Abstract :
An analog complementary bipolar IC process has been developed featuring 9.0-GHz fT npn and 5.5-GHz fT pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the HFE×VA of pnp transistors is 350 V with fT of 5.5 GHz and fmax of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz fT npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET´s and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability
Keywords :
bipolar integrated circuits; integrated circuit technology; linear integrated circuits; 5.5 GHz; 8.5 GHz; 9 GHz; Early voltage; NiCr; Schottky diodes; analog complementary bipolar IC technology; current gain; cutoff frequency; device optimization; laser wafer trimmable NiCr resistors; pnp transistors; process optimization; Analog integrated circuits; Bipolar integrated circuits; Costs; Cutoff frequency; Iron; Manufacturing processes; Performance gain; Schottky diodes; Transistors; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.293316
Filename :
293316
Link To Document :
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