DocumentCode :
1103919
Title :
Design and CAD for Nanotechnologies
Author :
Cheng, Tonglei
Volume :
24
Issue :
4
fYear :
2007
Firstpage :
300
Lastpage :
300
Abstract :
Recent innovations in nanoscale devices offer the potential for greater information density and system functionality. However, such devices present several new challenges. Design methodologies and tools have obtained a tremendous degree of sophistication and predictive value, and there are advantages in using the power of these tools to define a context for evaluating next-generation nanoelectronic technologies. Without a common context of systems evaluation, it will be difficult to make early viability assessments of new nanoelectronic-device approaches, nor will it be possible to strategically guide the development of these new technologies. This issue of IEEE Design & Test offers a special section on such topics. In addition, this issue presents the first in a series of tutorial articles derived from presentations at Test Technology Educational Program (TTEP) conferences. Finally, there are five general-interest articles on a wide range of topics.
Keywords :
CMOS technology; Circuit noise; Circuit testing; Design automation; Design methodology; Educational technology; Nanoscale devices; Parasitic capacitance; Propagation delay; Threshold voltage; CAD; CMOS; SEU; delay testing; process diagnosis; redundancy;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2007.130
Filename :
4293171
Link To Document :
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