Leakage Minimization Technique for Nanoscale CMOS VLSI

Author

Kim, Kyung Ki ; Kim, Yong-Bin ; Choi, Minsu ; Park, Nohpill

Author_Institution

Northeastern Univ, Boston

Volume

24

Issue

4

fYear

2007

Firstpage

322

Lastpage

330

Abstract

Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit design; leakage currents; low-power electronics; nanoelectronics; gate-tunneling; leakage power minimization technique; low-power digital circuit design; nanoscale CMOS VLSI circuit; power dissipation; reverse-biased junction band-to-band-tunneling leakage current; supply-threshold voltage scaling; Breakdown voltage; CMOS technology; Circuit testing; Leakage current; NP-hard problem; Power dissipation; Semiconductor device modeling; Subthreshold current; Tunneling; Very large scale integration; cell characterization; gate-tunneling current; input pattern generation; leakage power; nanometer CMOS; subthreshold leakage current;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2007.111

Filename

4293176