Title :
Variation-Tolerant, Power-Safe Pattern Generation
Author :
Devanathan, V.R. ; Ravikumar, C.P. ; Kamakoti, V.
Author_Institution :
Texas Instrum. India, Bangalore
Abstract :
By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the framework´s effectiveness.
Keywords :
logic testing; power grids; system-on-chip; SoC; benchmark circuit; power grid information; power-safe pattern generation; regional constraint; switching activity; Circuit faults; Circuit testing; Clocks; Debugging; Delay; Packaging; Power generation; Power supplies; Test pattern generators; Voltage; IR drop; low-power ATPG; peak power; power profiling; process variation;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2007.118
