Title :
Raisin: Redundancy Analysis Algorithm Simulation
Author :
Huang, Rei-Fu ; Li, Jin-Fu ; Yeh, Jen-Chieh ; Wu, Cheng-Wen
Author_Institution :
MediaTek, Chongqing
Abstract :
To increase redundancy repair efficiency and thus final yield in embedded- memory cores, we propose Raisin, a redundancy analysis algorithm simulation tool that can calculate an RA algorithm´s repair rate, yield, associated memory configuration, and redundancy structure. Raisin lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are essential for BISR of embedded memories.
Keywords :
embedded systems; memory cards; redundancy; system-on-chip; Raisin; embedded-memory cores; redundancy analysis algorithm simulation tool; redundancy repair efficiency; Algorithm design and analysis; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Design methodology; Electrical fault detection; Redundancy; Silicon; BIRA; BISR; Raisin; algorithm simulation; redundancy analysis; repair rate; yield;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2007.144
